Low power high speed hybrid CMOS Full Adder By using sub-micron technology

In the recent year, many other new circuits are proposed using less number of transistors with less delay and extremely low power requirement. An adder consisting with less transistors don't give full swing outputs for all input combinations and there is difference in output level for various combinations and these circuits have very low driving capabilities. other circuits also are proposed in but they are doing not give full swing output for all input combinations and power requirement is more.. The carry select adder is meant using hybrid CMOS full adder logic style and proposed full adder by dividing it in three modules in order that it are often optimized at various levels.[1] First module is an XOR-XNOR circuit, that generates full swing XOR and XNOR outputs at the same time and have an honest driving capability. It also consumes minimum power and provides better delay performance. Second module is total circuit that is additionally a X-OR circuit and uses carry input and also the output of the primary module as input to get total output. Third module may be a carry circuit which uses the output of the primary stage and other inputs to get carry output. within the new full adder design new full adder circuit is proposed which reduce the facility consumption, delay between perform to hold in and PDP by 10 to 100%. Simulations area unit disbursed on LT-PICE&ELECTRIC mistreatment TSMC 0.45μm CMOS Scale. So far designing the high performance arithmetic circuit’s minimization of the power and delay of the full adder circuit is required